Sunita Chandrasekaran

Ph.D.

Nanyang Technological University (NTU),

Computer Science Engineering,

Singapore

2006 - 2012

 

“Tools and Algorithms for High Level Algorithm Mapping to FPGA"

Field Programmable Gate Array (FPGA) provides the ability to use, and re-use, hardware with minimal re-development time. The current programming methodologies are explored for FPGAs, including the various techniques to raise the level of abstraction above register transfer level (RTL). However, it is a challenge to reduce the amount of manual programming necessary and still be able to achieve the required performance and speedup, let alone provide some improvement. The motivation of this thesis is to bridge the gap between the emerging FPGA hardware capability and the supporting software infrastructure. A design methodology (C2FPGA) is designed and developed. This methodology is used to generate hardware code without the need for an in-depth knowledge of a hardware descriptive language (HDL). This approach has been validated by performing several experiments on applications from different domains. Some promising results have been obtained and the capabilities of the proposed tool and its methodology have been demonstrated to address some of the programmability and productivity issues, effectively and efficiently.

 

B.E.

Anna University, 

Chennai (Madras), India

2001-2005

 

Major: Electrical and Electronics

Final year project, “Experimental Studies in Statistical Signal Processing”, from IIT, Madras, India.